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Memory Management – Study Guide
Quiz: Short-Answer Questions
Instructions:
Answer the following questions in 2–3 sentences based on the
provided material.
-
What is the fundamental difference between a logical address and a
physical address? -
Describe the three different stages at which address binding of
instructions and data to memory can occur. -
What is the purpose of the Memory-Management Unit (MMU) and how does
it use a relocation register? -
Explain the concept of swapping and the role of the backing store.
-
What is the difference between external and internal fragmentation?
-
Briefly describe the three main strategies for solving the dynamic
storage-allocation problem: first-fit, best-fit, and worst-fit. -
How does the paging memory-management scheme work by dividing
physical and logical memory? -
What performance issue is created by keeping the page table in main
memory, and how do translation look-aside buffers (TLBs) address
this? -
In the context of a page table, what is the function of the
valid-invalid bit? -
How does the segmentation memory-management scheme support a
user's view of memory?
Answer Key
1. A logical address, also called a virtual address, is generated by
the CPU. A physical address is the address seen by the memory unit.
They are the same in compile-time and load-time binding but differ in
execution-time binding.
2. Address binding can occur at compile time if memory locations
are known in advance, at load time if relocatable code is used, or at
execution time if processes can move during execution, requiring
hardware support.
3. The MMU is a hardware device that maps logical addresses to
physical addresses. It adds the value stored in the relocation
register to each logical address before accessing memory.
4. Swapping temporarily moves a process from main memory to a
backing store (disk) to free memory space. The process is later brought
back to continue execution.
5. External fragmentation occurs when free memory exists but is not
contiguous. Internal fragmentation occurs when allocated memory is
larger than needed, leaving unused space inside partitions.
6. First-fit allocates the first hole large enough. Best-fit
allocates the smallest hole that fits. Worst-fit allocates the largest
available hole.
7. Paging divides physical memory into frames and logical memory
into pages of the same size. A page table maps pages to frames,
allowing noncontiguous allocation.
8. Keeping the page table in main memory requires two memory
accesses per operation. TLBs cache recent translations, reducing this
to one access on a TLB hit.
9. The valid-invalid bit indicates whether a page belongs to a
process’s logical address space. Invalid pages trigger protection
faults.
10. Segmentation divides a program into logical units such as code,
stack, and data. This matches the user’s view of memory and is managed
using a segment table.
Essay Questions
Instructions:
Prepare to answer the following questions in detailed essay format.
-
Compare and contrast paging and segmentation in terms of allocation,
fragmentation, and hardware requirements. -
Explain the process from source code to in-memory binary image,
including the roles of the compiler, linker, and loader, and address
binding stages. -
Discuss advanced page table structures for large address spaces,
including hierarchical paging, hashed page tables, and inverted
page tables. -
Trace logical-to-physical address translation in the Intel Pentium
architecture, explaining segmentation and paging roles. -
Describe contiguous memory allocation, relocation registers, and
the dynamic storage-allocation problem. Compare first-fit,
best-fit, and worst-fit strategies.
Glossary of Key Terms
| Term | Definition |
|---|---|
| Address Binding | Associating instructions and data with physical memory addresses |
| Associative Memory | Fast-lookup hardware cache (TLB) |
| Backing Store | Disk used to store swapped-out processes |
| Base Register | Holds starting physical address of a process or segment |
| Best-fit | Allocates the smallest hole that fits |
| Compaction | Combines scattered free memory into one block |
| Contiguous Allocation | Each process occupies a single memory block |
| Dynamic Linking | Linking postponed until execution time |
| Dynamic Loading | Routines loaded only when called |
| Execution-Time Binding | Address binding done during execution |
| External Fragmentation | Free memory exists but is noncontiguous |
| First-fit | Allocates the first suitable hole |
| Frames | Fixed-size physical memory blocks |
| Hashed Page Tables | Page tables using hashing for large address spaces |
| Hierarchical Paging | Multi-level page tables |
| Hit Ratio (α) | TLB success rate |
| Hole | Free block of memory |
| Internal Fragmentation | Unused space inside allocated memory |
| Inverted Page Table | One entry per physical frame |
| Limit Register | Defines size of process or segment |
| Logical Address | Address generated by the CPU |
| MMU | Hardware mapping logical to physical addresses |
| Page Number (p) | Index into the page table |
| Page Offset (d) | Offset within a page |
| Page Table | Maps pages to frames |
| PTBR | Points to page table location |
| PRLR | Size of page table |
| Paging | Memory divided into pages and frames |
| Physical Address | Actual memory address |
| Relocation Register | Added to logical address for relocation |
| Segmentation | Memory divided into logical segments |
| Segment Table | Maps segments to physical memory |
| Shared Pages | Shared read-only code between processes |
| Swapping | Moving processes between memory and disk |
| TLB | Cache for page table entries |
| Valid-Invalid Bit | Indicates legal pages |
| Worst-fit | Allocates the largest hole |
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